1. Field of the Invention
The present invention relates to a power-up detection circuitry, and more particularly, to a power up detection circuit included in a semiconductor device which provides a stable power-up operation.
2. Description of the Related Art
When semiconductor devices such as semiconductor memory devices are powered on, such devices begin to operate only when an internal power supply voltage is greater than a predetermined voltage level ensuring stable operation. This function is performed by a power-up detection circuit. The power-up detection circuit provides an output signal to the internal circuits of the device, e.g., input/output circuits. Namely, when the internal power supply voltage is greater than a predetermined voltage level, the power-up detection circuit enables the memory device by activating an output signal VCCH.
Typically, stable operation of a semiconductor memory device cannot be ensured in a prior art power-up detection circuit when the internal power supply voltage VINT supplied to the device is less than a predetermined voltage level Va, as shown in FIGS. 1A and 1B. In particular, many semiconductor memory devices require a low voltage for their self-refresh operations. In those devices, it is impossible to set the predetermined voltage level Va to a higher level. For example, the output signal VCCH of the power-up detection circuit continues to be active during operation of the memory device, but it may become inactive due to the internal power supply voltage VINT dropping down to less than the predetermined voltage level Va to reduce power consumption during the self-refresh operation (shown by t.sub.SR in FIG. 1B). When this happens, master clocks such as the row address strobe signal /RAS become inactive causing discontinuous operation when the device is released from the self-refresh operation.
One solution to the above-mentioned problem is a power-up detection circuit having the operational characteristics shown in FIGS. 2A and 2B. It can be seen from FIGS. 2A and 2B that the output signal VCCH of the prior art power-up detection circuit becomes active when the internal power supply voltage is more than a first predetermined voltage level Va' and that the output signal VCCH becomes inactive when the internal power supply voltage VINT is less than a second predetermined voltage level Vi. In this circuit, however, the internal power supply voltage VINT fluctuates as shown in FIG. 2B. The internal power supply voltage might also drop down during a low-voltage mode such as the self-refresh operation (shown by t'.sub.SR in FIG. 2B). If the internal power supply voltage VINT temporarily drops to less than the second predetermined voltage level Vi, the memory device can prematurely end the self-refresh operation.